基本信息
李华伟  女  博导  中国科学院计算技术研究所
电子邮件: lihuawei@ict.ac.cn
通信地址: 海淀区科学院南路6号中科院计算所体系结构国家重点实验室
邮政编码: 100190

研究领域

集成电路设计自动化、近似计算、容错计算、设计验证与测试

教育背景

1999-07--2001-06   中国科学院计算技术研究所   博士学位
1996-09--1999-06   中国科学院计算技术研究所   硕士学位

工作经历

2008/10-今,中科院计算所,计算机体系结构国家重点实验室, 研究员
2009/08-2010/08,美国UCSB大学,电子与计算机工程系,访问教授
2001/10-2008/09,中科院计算所,网络室/中科院计算机系统结构重点实验室,副研究员(2002/03硕士生导师,2006/03博士生导师)
2001/07-2001/09,中科院计算所,网络室,助理研究员

社会兼职
2016-01-01-今,中国计算机学会容错计算专委会, 主任
2016-01-01-今,中国计算机学会, 理事
2014-12-31-2018-12-31,IEEE TVLSI期刊编委, Associate Editor
2014-01-01-今,《计算机研究与发展》编委,
2010-01-01-今,《计算机辅助设计与图形学学报》编委,
2007-12-30-2015-12-31,中国计算机学会容错专业委员会, 秘书长

发表论文

[1]    Ying Wang, Yinhe Han, Cheng Wang, Huawei Li, Xiaowei Li, “Retention-Aware DRAM Assembly and Repair for Future FGR Memories”, IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 36, No.5, pp.705-718, 2017.

[2]    Jian Wang, Huawei Li, Tao Lv, Tiancheng Wang, Xiaowei Li, and Sandip Kundu, “Abstraction-Guided Simulation Using Markov Analysis for Functional Verification,” IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 35, No.2, pp.285-297, 2016.

[3]    Yanhong Zhou, Tiancheng Wang, Huawei Li, Tao Lv, Xiaowei Li, “Functional Test Generation for Hard-to-reach States Using Path Constraint Solving,” IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 35, No.6, pp.999-1011, 2016.

[4]    Guihai Yan, Faqiang Sun, Huawei Li, Xiaowei Li, “CoreRank: Redeeming Imperfect Silicon by Dynamically Quantifying Core-level Healthy Condition of Manycore Processors”, IEEE Transactions on Computers (TC), Vol. 65, No.3, pp.716-729, 2016.

[5]    Yun Cheng, Huawei Li, Ying Wang, Yingke Gao, Bo Liu, Xiaowei Li, “Flip-flop Clustering based Trace Signal Selection for Post-Silicon Debug,” Proc. of IEEE VLSI Test Symposium (VTS'17), Paper 3A-2, USA, April 2017.

[6]    Ying Wang, Huawei Li, Xiaowei Li, “Re-architecting the On-chip memory Sub-system of Machine-Learning Accelerator for Embedded Devices,” Prof. of IEEE International Conference On Computer Aided Design (ICCAD'16), USA, Nov. 2016.

[7]    Ying Wang, Jie Xu, Yinhe Han, Huawei Li, Xiaowei Li, “DeepBurning: Automatic Generation of FPGA-based Learning Accelerators for the Neural Network Family”, IEEE/ACM Proceedings of Design, Automation Conference (DAC'16), USA, 2016.

[8]    Ying Wang, Yinhe Han, Jun Zhou, Huawei Li, Xiaowei Li, “DISCO: A Low Overhead In-Network Data Compressor for Energy-Efficient Chip Multi-Processors”, IEEE/ACM Proceedings of Design, Automation Conference (DAC'16), USA, 2016.

[9]    Huina Chao, Huawei Li, Tiancheng Wang, Xiaowei Li and Bo Liu, “An accurate algorithm for computing mutation coverage in model checking,” Prof. IEEE International Test Conference (ITC'16), USA, Paper 16.2, Nov. 2016.

[10] Yanhong Zhou, Huawei Li, Tiancheng Wang, Bo Liu, Yingke Gao, Xiaowei Li, “Path Constraint Solving based Test Generation for Observability-enhanced Branch Coverage,”, Proc. of IEEE VLSI Test Symposium (VTS'16), Paper 1B-2, USA, April 2016.

[11] Ying Wang, Yinhe Han, Huawei Li, Lei Zhang, Yuanqing Cheng, Xiaowei Li, “PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3D Die-Stacked PCM”, IEEE Transactions on Very Large Scaled Integration Systems (TVLSI), Vol.24, No.5, pp.1613-1625, 2016.

[12] Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li, “Data Remapping for Static NUCA in Degradable Chip Multiprocessors”, IEEE Transactions on Very Large Scaled Integration Systems (TVLSI), Vol. 23, No.5, pp. 879-892, 2015.

[13] Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li, “Economizing TSV resources in 3D Network-on-Chip design”, IEEE Transactions on Very Large Scaled Integration Systems (TVLSI), Vol. 23, No.3, pp. 493-506, 2015.

[14] Dawen Xu, Huawei Li, Amirali Ghofrani, K.-T. Cheng, Yinhe Han, Xiaowei Li, “Test-Quality Optimization for Variable n-Detections of Transition Faults,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.22, No.8, pp. 1738-1749, August 2014.

[15] Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li, “ZoneDefense: A Fault-Tolerant Routing for 2D Meshes Without Virtual Channels,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.22, No.1, pp.113-126, 2014.

[16] Yuntan Fang, Huawei Li, and Xiaowei Li, “Lifetime enhancement techniques for PCM-based image buffer in multimedia applications,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.22, No.6, pp. 1450-1455, June 2014.

[17] Song Jin, Yinhe Han, Huawei Li, Xiaowei Li, “Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.21, No.5, May 2013, pp.821-833.

[18] Ying Zhang, Huawei Li, Xiaowei Li, “Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.21, No.7, July 2013, pp.1220-1233.

[19] Zijian He, Tao Lv, Huawei Li, Xiaowei Li, “Test Path Selection for Capturing Delay Failures Under Statistical Timing Model,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.21, No.7, July 2013, pp.1210-1219.

[20] Yuntan Fang, Huawei Li, Xiaowei Li, “RSAK: Random Stream AttacK for Phase Change Memory in Video Applications,” Proc. of IEEE VLSI Test Symposium (VTS'13), Paper 10B-3, Berkeley, CA, USA, May 2013.

[21] Xiang Fu, Huawei Li, Xiaowei Li, “Testable path selection and grouping for faster than at-speed testing,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.20, No.2, 2012, pp.236-247.

[22] Songwei Pei, Huawei Li, Xiaowei Li, “Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.20, No.12, 2012, pp. 2157-2169.

[23] Songwei Pei, Huawei Li, Xiaowei Li, “A High-Precision On-Chip Path Delay Measurement Architecture,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.20, No.9, 2012, pp.1565-1577.

[24] Ying Zhang, Huawei Li, Yinghua Min, Xiaowei Li, “Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.19, No.10, 2011, pp.1787-1800.

[25] Minjin Zhang, Huawei Li, Xiaowei Li, “Path Delay Test Generation Toward Activation of Worst Case Coupling Effects,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.19, No.11, 2011, pp.1969-1982.

[26] Songwei Pei, Huawei Li, and Xiaowei Li, “A Unified Test Architecture for on-Line and Off-Line Delay Fault Detections", Proc. IEEE VLSI Test Symposium (VTS'11), 2011, pp.272-277.

[27] Huawei Li, Dawen Xu, K.-T. Cheng, “GPU-accelerated fault simulation and its new applications,” Proc. 2011 International Symposium on VLSI Design, Automation and Test (V LSI-DAT), invited paper in Special Session I (GPU Applications), Taiwan, April 2011.

[28] Huawei Li, Dawen Xu, Yinhe Han, K.-T. Cheng, Xiaowei Li, “nGFSIM: A GPU-Based 1-to-n-Detection Fault Simulator and its Applications,” Proc. IEEE 41st International Test Conference (ITC'10), Paper 12.1, Austin, USA, Oct. 2010.

[29] Zijian He, Tao Lv, Huawei Li, Xiaowei Li, “Fast path selection for testing of small delay defects considering path correlations,” Proc. of IEEE 28th VLSI Test Symposium (VTS'10), Santa Cruz, USA, May 2010, pp.3-8.

[30] Songwei Pei, Huawei Li, Xiaowei Li, “An On-Chip Clock Generation Scheme for Faster than-at-Speed Delay Testing”, Proc. of Design Automation and Test in Europe (DATE'10), France, Mar. 2010, pp.1353-1356.

[31] Huawei Li, Peifu Shen, and Xiaowei Li, “Robust Test Generation for Crosstalk-Induced Path Delay Faults,” 24th IEEE VLSI Test Symposium (VTS'06), Berkeley, CA, USA, May 2006.

[32] Huawei Li, and Xiaowei Li, “Selection of Crosstalk-induced Faults in Enhanced Delay Test,” Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 21, No.2, 2005, pp.181-195.

[33] Huawei Li, Yue Zhang, and Xiaowei Li, “Delay Test Pattern Generation Considering Crosstalk-induced Effects,” IEEE 12th Asian Test Symposium (ATS'03), Xi'an, China, Nov. 2003, pp.178-183.

[34] Huawei Li, Zhongcheng Li, and Yinghua Min, “Reduction of Number of Paths to be tested in Delay Testing,” Journal of Electronic Testing: Theory and Applications, Vol.16, No.5, Oct. 2000, pp. 477-485.

学术奖励

  1. 2012年度国家技术发明奖二等奖,获奖项目:星载微处理器系统验证-测试-恢复技术及应用

  2. 2014年度北京市科学技术奖一等奖,获奖项目:“32位星载容错控制计算机系统关键技术及应用

  3. 2011年度中国质量协会质量技术奖一等奖,获奖项目:高性能处理芯片的测试和可靠性设计关键技术

  4. 2008年度中国科学院卢嘉锡青年人才奖,2012年入选中国科学院青年创新促进会成员

  5. 2008年度中国计算机学会王选奖二等奖,获奖项目:数字电路测试若干关键技术及其在微处理器测试中的应用

  6. 2008年度北京市科学技术奖(发明类)三等奖,获奖项目:数字电路实速检测和故障诊断技术及其应用

  7. 2007年度北京市科学技术奖(基础研究类)三等奖,获奖项目:集成电路逻辑测试与验证基础技术

  8. 2003年度中国科学院杰出科技成就奖,获奖团队:龙芯CPU”研究集体

  9. 2004年度全国优秀博士论文提名:基于RTL行为模型的测试产生及时延测试方法

  10. 2001年度中国科学院院长奖学金特别奖

近期科研项目

国家自然科学基金重点项目:差错容忍计算器件基础理论和方法,2015/01-2019/12。

国家自然科学基金面上项目:考虑时延变异性的硅后定时验证方法,2012/01-2015/12。

国家973课题:高性能处理芯片的设计验证与测试,2005/12-2010/12。

国家自然科学基金面上项目:避免过度测试的时延测试方法,2008/01-2010/12。

国家自然科学基金面上项目:面向串扰的时延测试,2007/01-2009/12。

国家863项目:可信计算平台软硬件系统安全测试评估模型、测试方法以及测试自动化技术,2007/07-2009/12。